Design Parameters for a Bit-Synchronized Transmission System

dc.contributor.author	Kundaeli, Herald N.
dc.date.accessioned	2016-09-29T14:52:25Z
dc.date.accessioned	2026-07-16T19:21:36Z
dc.date.available	2016-09-29T14:52:25Z
dc.date.issued	1993
dc.description	Full text can be accessed at http://www.tandfonline.com/doi/abs/10.1080/00207219308907118	en_US
dc.description.abstract	The transmission reliability of transmission systems that employ synchronization codes For frame synchronization has been analysed in a previous report (Kundaeli 1991) in which it was shown that the introduction of verify states in the synchronization recovery and loss paths of the receiver resulted in increased reliability. Here we extend that analysis to provide a general method for determining the receiver design and performance parameters. We first derive the synchronization efficiency as a new performance parameter, then the applicable number of verify states for a receiver for practical ranges of both the channel error-rate and frame length.	en_US
dc.identifier.citation	Kundaeli, H.N., 1993. Design parameters for a bit-synchronized transmission system. International Journal of Electronics Theoretical and Experimental, 75(3), pp.393-405.	en_US
dc.identifier.doi	10.1080/00207219308907118
dc.identifier.uri	https://libraryrepository.udsm.ac.tz/handle/123456789/416
dc.language.iso	en	en_US
dc.publisher	Taylor & Francis	en_US
dc.title	Design Parameters for a Bit-Synchronized Transmission System	en_US
dc.type	Journal Article, Peer Reviewed	en_US

Files

Now showing 1 - 1 of 1