Browsing by Author "Singh, Ngangbam Phalguni"

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    Investigation of power dissipation in data selective flips flops triggered by octree clocking technique for low power buffer design
    (University of Dar es salaam, 2019) Singh, Ngangbam Phalguni
    In the past few decades, studies have demonstrated that power dissipation is one of the key challenges in information and communication technology (ICT) devices. The main factors are memory storage elements, the log elements and the clocking technique. It leads to heating effect on the devices after prolonged usage. In such an application flip flop with proper clocking system can be used to design low power buffer, which can reduce the power dissipation. This thesis presents a quantitative research investigating the power dissipation in various data selective flip flops. A ring counter, with octree clocking system and combinational elements (C-Elements), is developed to control the clock signals triggering the flip flops and avoid unwanted switching activities during redundant events. Buffers are accessed in the form of ring counters, which control data transfer between chips in the computer internal circuits. The viability of the design is verified by the simulation using very High-Speed Hardware Description language (VHDL) programs with Altera’s Quartus II and Xilinx’s ISE. Analog current and transient analyses are done using Multisim 8 tools. Simulation results show that the deployed technique reduction on power dissipation by 44.08% and 14.20% with respect to fixed body biased and static random access memory (SRAM) respectively. Simulation results also show that the designed buffer dissipates 1.655 nW in 2 stage and 0.666 mW in 64 bit delay buffer using octree clocking techniques with DDFF is 14.72%.
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    Investigation of power dissipation in data selective flips flops triggered by octree clocking technique for low power buffer design
    (University of Dar es Salaam, 2019) Singh, Ngangbam Phalguni
    In the past few decades, studies have demonstrated that power dissipation in one of the key challenges ‘’in Information and Communication Technology (ICT) devices. The main factors are memory storage elements, the logic elements and the clocking technique. It leads to heating effect on the devices after prolonged usage. In such an application, flip flop with proper clocking system can be to design low power buffer, which can reduce the power dissipation. This thesis presents a qualitative research investigating the power dissipation in various data selective flip flops. A ring counter, with octree clocking system and Combinational Elements (C-Elements), is developed to control the clock signals triggering the flip flops and avoid unwanted switching activities during redundant events. Buffers are accessed in the form of ring counters, which control data transfer between chips in the computer internal circuits. The viability of the design is verified by the simulation using Very High-Speed Hardware Description Language (VHDL) programs with Altera’s Quartus II and Xilinx’s ISE. Analog current and transient analysis are done using Multisim 8 tools. Simulation results show that the deployed technique provides reduction on power dissipation by 44.08% and 14.20% with respect to fixed body biased and static Random Access Memory (SRAM) respectively. Simulation results also show that the designed buffer dissipates 1.655 nW in 2 stage and 0.666 mW in 64 bits. The improvement in 64 bit delay buffer Octree clocking technique with DDFF is 14.72%.